1. Field of the Invention
The present invention relates to a shift-register circuit, and more particularly, to a shift-register circuit for a liquid crystal display.
2. Description of the Related Art
FIG. 1 shows a conventional shift-register circuit as disclosed by U.S. Pat. No. 4,084,106 of Ullrich in 1978. FIG. 1 shows only a single shift-register unit, although a plurality of shift-register units comprises a shift-register circuit. An inverse clock signal XCK is coupled to the gate of three NMOS transistors Q1xcx9cQ3. Each of the NMOS transistors Q1xcx9cQ3 has a gate capacitor Cg.
The dynamic power loss of the inverse clock signal is obtained as follows:
P=fcv2; 
wherein P is dynamic power loss, f is the frequency of the inverse clock signal, c is the total parasitic capacitance on the clock bus, and the v is the voltage swing of the inverse clock signal, where the total capacitance c includes gate capacitors of transistors coupled to the inverse clock signal. When capacitor Cg increases continuously, the dynamic power loss also increases.
It is therefore an object of the present invention to provide a shift-register circuit for reducing the number of parasitic capacitors of transistors coupled to a clock signal.
To achieve the above-mentioned object, the present invention provides a shift-register circuit having a plurality of shift-register units connected in serial enabling transmission of a clock signal, an inverse clock signal, and a first voltage. Each shift-register unit comprises, an inverter and first, second, third and fourth transistors. The first transistor includes a gate coupled to the inverse clock signal, and a first source/drain coupled to a signal output from a previous-stage shift-register unit. The inverter includes a first input terminal coupled to the first source/drain of the first transistor. The second transistor includes a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to the clock signal, and a second source/drain coupled to an output terminal. The third transistor includes a gate coupled to a first output terminal of the inverter, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage. The fourth transistor includes a gate coupled to a signal output from a next-stage shift-register unit, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage.
In addition, the present invention provides another shift-register circuit having a plurality of shift-register units connected in serial for a clock signal, an inverse clock signal, and a first voltage. Each shift-register unit comprises, an inverter and first, second, third and fourth transistors. The first transistor includes a gate coupled to the inverse clock signal, and a first source/drain coupled to a signal output from a previous-stage shift-register unit. The second transistor includes a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to the clock signal, and a second source/drain coupled to an output terminal. The inverter includes a first input terminal coupled to the output terminal. The third transistor includes a gate coupled to a first output terminal of the inverter, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage. The fourth transistor includes a gate coupled to a signal output from a next-stage shift-register unit, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage.
The present invention provides another shift-register circuit having a plurality of shift-register units connected in serial for a clock signal, an inverse clock signal, and a first voltage. Each shift-register unit comprises, an inverter, a control device and first, second, third and fourth transistors. The first transistor includes a gate coupled to the inverse clock signal, and a first source/drain coupled to a trigger terminal. The inverter includes a first input terminal coupled to the first source/drain of the first transistor. The second transistor includes a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to the clock signal, and a second source/drain coupled to an output terminal for outputting signals. The third transistor includes a gate coupled to a first output terminal of the inverter, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage. The fourth transistor includes a gate coupled to a reset terminal, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage. The control device controls directs the output signal of the shift-register circuit left or right and comprises a seventh, a eighth, a ninth and a tenth transistors. The seventh transistor includes a gate coupled to a left signal directing the output signal of the shift-register circuit left, a first source/drain coupled to a signal output from a previous-stage shift-register unit, and a second source/drain coupled to the reset terminal. The eighth transistor includes a gate coupled to the left signal, a first source/drain coupled to a signal output from a next-stage shift-register unit, and a second source/drain coupled to the trigger terminal. The ninth transistor includes a gate coupled to a right signal for directing the output signal right, a first source/drain coupled to the output signal output from the previous-stage shift-register unit, and a second source/drain coupled to the trigger terminal. The tenth transistor includes a gate coupled to a right signal, a first source/drain coupled to the output signal output from the next-stage shift-register unit, and a second source/drain coupled to the reset terminal.
The present invention additionally provides another shift-register circuit having a plurality of shift-register units connected in serial enabling transmission of a clock signal, an inverse clock signal, and a first voltage. Each shift-register unit comprises, an inverter, a control device and first, second, third and fourth transistors. The first transistor includes a gate coupled to the inverse clock signal, and a first source/drain coupled to a trigger terminal. The second transistor includes a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to the clock signal, and a second source/drain coupled to an output terminal for outputting signals. The inverter includes a first input terminal coupled to the output terminal. The third transistor includes a gate coupled to a first output terminal of the inverter, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage. The fourth transistor includes a gate coupled to a reset terminal, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage. The control device controls directs the output signal of the shift-register circuit left or right and comprises seventh, eighth, ninth and tenth transistors. The seventh transistor includes a gate coupled to a left signal directing the output signal of the shift-register circuit leftward, a first source/drain coupled to a signal output from a previous-stage shift-register unit, and a second source/drain coupled to the reset terminal. The eighth transistor includes a gate coupled to the left signal, a first source/drain coupled to a signal output from a next-stage shift-register unit, and a second source/drain coupled to the trigger terminal. The ninth transistor includes a gate coupled to a right signal for directing the output signal right, a first source/drain coupled to the output signal output from the previous-stage shift-register unit, and a second source/drain coupled to the trigger terminal. The tenth transistor includes a gate coupled to a right signal, a first source/drain coupled to the output signal output from the next-stage shift-register unit, and a second source/drain coupled to the reset terminal.